1. Field of Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device which forms a capacity coupling between a power source voltage VDD and a power source voltage VSS by an FET provided inside a gate array.
2. Description of Related Art
FIG. 1 shows a conventional gate array GA. A plurality of gates is arranged all over the gate array GA shown in FIG. 1(A). As shown in FIG. 1(B), a basic cell BC is arranged at regular intervals covering the region where the gates are arranged. As shown in FIG. 1(c), the basic cell usually has either four or eight FET. The desired circuit can be obtained by connecting the FET inside the basic cell BC by an aluminum wire.
FIG. 2 shows conventional inverters INV10 and INV12, and also shows the current, which flows between the inverter INV10 and the inverter INV12. The inverter INV10 and the inverter INV 12 are formed by the FET inside the basic cell BC. A signal line LIN connects the inverter INV10 and the inverter INV12. As shown in FIG. 2(A), when the voltage Vout, which is a voltage output from inverter INV10, inverts from a Low signal to High signal, a power source current Ih flows from the power source voltage VDD to the signal line LIN. A wiring capacitance CL is generated in the signal line LIN, so that a part of the power source current Ih is consumed in charging the wiring capacitance CL. A pass-through current Ihl flows in the inverter INV10 from the power source voltage VDD to the power source voltage VSS.
As shown in FIG. 2(B), when the voltage Vout, which is a voltage output from the inverter INV10, inverts from a High signal to Low signal, a pass-through current Ihl flows in the inverter INV10 from the power source voltage VDD to the power source voltage VSS. Because the electric charge, which is charged in the wiring capacitance CL, discharges, a power source current Il flows from the wiring capacitance CL to the power source voltage VSS of the inverter INV10.
FIG. 3 shows the waveform of the voltage input or output from the inverter INV10. FIG. 3(A) shows the waveform of the voltage Vin, which is the voltage input to the inverter INV10.
FIG. 3(B) shows the waveform of the voltage Vout, which is the voltage output from the inverter INV10. FIG. 3(C) shows the waveform of the voltage VDD-VSS, which is the voltage obtained by subtracting the power source voltage VSS from the power source voltage VDD. As shown ain A of FIG. 3(A), if the voltage Vin inverts from a Low signal to High signal, the voltage Vout inverts from a High signal to Low signal as shown in A of FIG. 3(B).
When the electric charge, charged in the wiring capacitance CL of the signal line LIN, discharges, the power source current Il flows from the wiring capacitance CL to the power source voltage VSS of the inverter INV10. Because the electric charge, which is charged in the wiring capacitance CL, is discharged to the power source voltage VSS, the voltage VDD-VSS decreases for a moment as shown in A of FIG. 3(C). Therefore, the decrease of the voltage Vout, which is output from the inverter INV10, is delayed.
Moreover, as shown in B of FIG. 3(A), if the voltage Vin inverts from a High signal to Low signal, the voltage Vout inverts from a Low signal to High signal as shown in B of FIG. 3(B). The power source current Ih flows from the power source voltage VDD of the inverter INV10 to the signal line LIN. Because the wiring capacitance CL is generated in the signal line LIN, the power source current Ih is consumed for charging the wiring capacitance CL. The wiring capacitance CL consumes the power source current Ih, so the voltage VDD-VSS decreases for a moment as shown in B of FIG. 3(C). Therefore, the increase of the voltage Vout delays as shown in FIG. 3(B). The timing of which of the circuits inside a gate array operates lags by the fluctuation of the power source voltage VDD and VSS generated by the charging and discharging of the wiring capacitance CL. The result is, a decrease in the accuracy of the timing of the operation.